The present invention relates generally to driving circuits and methods, and more particularly, to systems, methods and apparatus for timing the conductance of driver circuits.
FIG. 1A is a typical driver circuit 100. A PMOS high side transistor Q1 is connected in series with an NMOS low side transistor Q2. The respective input nodes 101 and 102 of the high side transistor Q1 and the low side transistor Q2 are cross coupled through respective driver/gates 111, 113 and 112, 114, so that as high side transistor begins to shut off (i.e., stop conducting), the low side transistor is gated to on (i.e., begin conducting). Transistor Q1 is a PMOS transistor and transistor Q2 is a NMOS transistor in the present example, however, the types of transistors can vary.
However, due to various circuit dynamics, such as parasitic capacitance, slow gate turn off ramp and other issues, one high side transistor does not turn off and stop conducting instantaneously and before one low side transistor turns on and begins conducting. FIGS. 1B and 1C are graphical representations of gate voltages applied to the typical driver circuit 100. In an initial state, transistor Q1 is non-conducting (state 0) and transistor Q2 is conducting (state 1).
A Q2 gate voltage 122 has an initial value for fully conducting state 1 at time T0. The Q2 gate voltage 122 has a downward slope as the Q2 gate voltage gradually decreases between time T0 and time T4. At time T0, the Q2 gate voltage 122 is enabled. However, the Q2 gate voltage 122 does not drop to minimum level Vmin, instantaneously as discussed above. At a time T3, the Q2 gate voltage 122 drops below a threshold voltage VTN for transistor Q2 and Q2 stops conducting. The Q2 gate voltage 122 continues to decrease to the minimum voltage Vmin at time T4.
Similarly, a Q1 gate voltage 121 has an initial value for fully non-conducting state 0. Q1 gate voltage 121 has a downward slope as the gate voltage gradually decreases between time T1 and time T5. At time T1, the Q1 gate voltage 121 is disabled or removed. However, the Q1 gate voltage 121 does not drop to minimum level Vmin instantaneously, as discussed above. At a time T2, the Q1 gate voltage 121 drops below a threshold voltage VTP for transistor Q1 and Q1 begins conducting. The Q1 gate voltage 121 continues to drop to minimum level Vmin at time T5 and Q1 continue to conduct between time T2 and beyond time T5.
As shown above, transistor Q2 is still conducting between time T2 and time T3 and therefore, when transistor Q1 begins conducting at time T2, then a current spike can occur through the series transistors Q1, Q2 until time T3, when Q2 stops conducting. The current spike consumes excess power and can cause component damage.
FIG. 1C illustrates the inverse of the switching sequence shown in FIG. 1B. The inverse switching sequence can result in a second current spike when transistor Q2 begins conducting at time T8 before the transistor Q1 stops conducting and time T9.
What is needed is a system and method to confirm the presently conducting transistor is actually in a fully non-conducting state 0 before the presently non-conducting transistor actually begins conducting and thus prevent the series current spikes described above between times T2 and T3 and between times T8 and T9.